One of the challenges of electronic system design is distributing a clock signal throughout the system. System designers generally use two architecture types to distribute the clock signal to various parts of the system. In a first clock distribution architecture, all of the clocks in the system are generated by a central clock source (or generator) and routed by board traces to wherever the clocks are needed. In a central clock source system, synchronizing all the clocks is not difficult since all the clocks are derived from the same source. However, the board designer needs to be careful to shield or isolate the clock lines from sources of noise. In addition, driving the traces takes a non-trivial amount of power from the central clock generator.
In a second commonly used clock distribution architecture, many different clock sources (generators) are scattered throughout the system, each placed near the chips to be driven by the different clock sources. In distributed clock systems, clock routing is straightforward and clock degradation is minimal since the transmission path is very short. However, since all of the distributed clock sources operate completely independently in the conventional distributed clock architecture, synchronization is not possible.
It would be desirable to implement wirelessly synchronized clock networks.